1. Field of the Invention
The present invention is directed to a low-capacitance (i.e., less than 10 pF) multi-layer varistor having a ceramic body and two terminals that are applied on the ceramic body at a distance from one another.
2. Description of the Related Art
Up to now, spark gaps that, for example, can be realized by two tips of an interconnect lying opposite one another, have preferably been utilized for the electrostatic or electrostatic discharge (ESD) protection of high-frequency circuits and data lines. When an impermissibly high voltage occurs for a high-frequency circuit or data line to be protected, the spark gap between the two tips of the interconnect lying opposite one another ignites, carrying an arcing discharge, so that this impermissibly high voltage is not adjacent at the high-frequency circuit or data line.
The ignition of the spark gap occurs according to specific physical laws in which the gas discharge characteristic is specifically traversed. This event requires a specific time duration so that the time alone that is needed for the ionization of the spark gap is usually longer than the rise time of an ESD pulse, which can lie on the order of magnitude of 700 ps.
In summary, this means that, due to their inertia, spark gaps have disadvantages when used as ESD protection of high-frequency circuits or data lines.
Compared to spark gaps, multi-layer varistors are characterized by a substantially shorter response time: the response time of multi-layer varistors are on the order or magnitude of 500 ps, which is lower by approximately a factor of 2 than the response time of spark gaps. Nonetheless, multi-layer varistors have previously not been utilized as ESD protection of high-frequency circuits or data lines, because of the laminar structure of the multi-layer varistors. This laminar structure, namely, leads to parasitic capacitances that make the use of multi-layer varistors impossible in high-frequency circuits with frequencies above 100 MHz. Such high-frequency circuits are, for example, high-frequency input circuits such as antenna inputs, etc.
FIGS. 13 through 15 show an existing multi-layer varistor in perspective (see FIG. 13), in section (see FIG. 14) or in an overall view with inner electrodes conducted out (see FIG. 15).
Given this multi-layer varistor, a ceramic body 1 is provided with terminals 8 at two opposite sides, these overlapping in the ceramic body 1 spaced from one another. Active zones 9 are formed in the overlap regions, and insulation zones 11 are provided outside the overlap regions 9.
FIG. 15 shows an element of the multi-layer varistor of FIG. 14: a layer of the ceramic body 1 is placed between two inner electrodes 7 that respectively form metallized surfaces 12 on this layer.
Such existing multi-layer varistors are poorly suited as ESD protection of high-frequency circuits and data lines because of their capacitance. In a given ceramic material having a defined dielectric constant E, this capacitance is determined by the area of the inner electrodes 7 or of the terminals 8, by the number of layers of the ceramic body 1 between the inner electrodes 7, i.e., by the number of active zones 9, and the thicknesses of the ceramic layers or active zones deriving as a result of the desired operating voltage.
Up to now, multi-layer varistors manufactured in such a technology have had capacitances on the order of magnitude of at least 30 through 50 pF, which precludes the use of such multi-layer varistors for the ESD protection of, for example, sensitive antenna inputs despite their low response time.
It is therefore an object of the present invention to create a multi-layer varistor that is distinguished by such a low capacitance that it can be employed without further effort for ESD protection in high-frequency circuits such as, in particular, antenna inputs.
This object is inventively achieved (in a low-capacitance multi-layer varistor having a ceramic body and two terminals that are applied on the ceramic body at a distance from one another) in that the ceramic body is built up using a film technique with a multi-layer structure. Expediently, the ceramic body is provided with inner electrodes that proceed comb-like from the two terminals so that the ends of the electrodes lie opposite one another with a gap (or spacing) in the direction between the terminals.
Given the inventive multi-layer varistor, the inner electrodes are, in particular, arranged comb-like, so that the electrodes of the two terminals no longer overlap but have their ends lying opposite one another. The low capacitance of the multi-layer varistor is thus determined via the spacing of these ends of the electrodes lying opposite one another (the xe2x80x9cgapxe2x80x9d). Given a constant or nearly constant gap, the capacitance can be reduced further by a serial arrangement of the gaps. In the limiting case, the varistor voltage can even be increased further and the capacitance reduced when inner electrodes are completely foregone. The influence of the terminals or outside termination on the varistor voltage and on the capacitance that is present in this limiting case can be eliminated by applying an additional passivation layer so that the maximum varistor voltage for a given volume can be achieved given minimal capacitance in such an exemplary embodiment.
The inner electrodes can be designed with different electrode lengths. It is also possible to shape the tips of the inner electrodes differently from one another.
Due to the non-overlapping inner electrodes, the electrode spacing can be considerably enlarged in the inventive multi-layer varistor, which correspondingly reduces the capacitance. As a result of the inner electrodes lying opposite one another, the direction of the current flow in the inventive multi-layer varistor is also modified compared to the existing multi-layer varistor, thus enabling a drastic increase in the varistor voltage.
Experiments by the inventors have shown that the curve of the current density can be positively influenced in the inventive multi-layer varistor due to the indicated arrangement of the inner electrodes. It is thus possible to manufacture a multi-layer varistor with a non-linear voltage/current characteristic that is high-impedance at voltages of, for example, 300 V and above.